1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to a transistor and method for producing a transistor by depositing thin silicon layers and forming thin dielectric sidewall spacers from the deposited silicon layers.
2. Description of the Relevant Art
The use of sidewall spacers to create lightly-doped drain (LDD) regions is a well established technique in MOSFET fabrication. The LDD regions reduce the maximum electric field at the drain/channel interface in the MOSFET. This reduction in electric field reduces the kinetic energy gained by electrons in the MOSFET channel, thereby mitigating undesirable "hot-carrier" effects. These hot-carrier effects include avalanche breakdown at the drain/substrate junction and injection of carriers into the gate dielectric.
The formation of lightly-doped drain regions according to a conventional process is illustrated in FIGS. 1-4. A gate conductor 12 having a pair of sidewalls 17 is patterned upon a semiconductor substrate 10 which is covered with a gate dielectric layer 11, as shown in FIG. 1. The semiconductor substrate is typically single-crystal silicon doped n-type or p-type, the gate dielectric is typically silicon dioxide, and the gate conductor is typically polysilicon. An impurity implant 8 self-aligned to the sidewalls 17 of the gate conductor 12 is typically performed in order to form lightly-doped regions 14 adjacent to the channel of the transistor. The implanted impurity is chosen so that the doping of the lightly-doped regions 14 is of opposite type than that of the semiconductor substrate 10. dielectric layer 13, typically silicon dioxide ("oxide"), is then conformally deposited over the gate conductor 12 and the exposed upper surface of gate dielectric 11 by chemical vapor deposition (CVD), as shown in FIG. 2. This oxide layer is then anisotropically etched so that the oxide is preferentially removed from horizontal surfaces, leaving oxide spacers 15 adjacent to the sidewalls 17 of the gate conductor, as shown in FIG. 3. A second impurity implant 9, self-aligned to exposed lateral surfaces of sidewall spacers 15, forms heavily-doped source and drain regions 16 which are displaced from gate conductor 12 by the width of a sidewall spacer 15, as shown in FIG. 4. The lightly-doped region directly under the sidewall spacer at the drain end of the channel reduces the maximum electric field in the device, but the lightly-doped regions also increase the series resistance encountered by electrons or holes traveling from the source to the drain.
As overall dimensions of transistors in integrated circuits are continually shrinking, the lateral widths of sidewall spacers must decrease as well. Excessively wide sidewall spacers result in correspondingly wide lightly-doped regions at the drain and source ends of the channel, which unnecessarily increase the series resistance of the transistor, resulting in decreased saturated drain current and transconductance. Because the conformality of CVD dielectric films is not perfect, sidewall spacers are difficult to form reliably with lateral widths of less than about 400 angstroms, or 0.04 microns. MOSFET gate widths are currently approaching 0.1 microns, so that sidewall spacer widths may comprise a significant portion of the path length between the source and drain regions. It is therefore possible that significant reductions in series resistance may be achieved by making ultrathin (about 200 angstroms wide or less) sidewall spacers. It would therefore be desirable to develop a method for reliably forming such ultrathin sidewall spacers for MOSFET fabrication.